Non-Volatile Dual In-Line Memory Modules (NVDIMMs) using Dual Data Rate (DDR) channels require asynchronous handshakes via a transaction-based interface. This handshake, which may also be used by other forms of memory other than NVDIMMs, may have variable read/write timing, and feedback information from the DIMM is required. In addition, some systems want to exchange metadata (request ID, hit/miss information, vendor metadata, etc.) between the host and DIMM. A dedicated channel to deliver metadata would require a hardware change, but using a dedicated package to deliver metadata would increase the performance overhead.
It is possible to exchange metadata using bits allocated for Error Correcting Codes (ECCs). U.S. Patent Publication No. 2014/0040550 to Nale et al. and assigned to Intel Corp. describes one approach to use ECC bits for metadata. In this solution, there is a “near/far” asynchronous memory hierarchy that requires metadata information transfers, and a protocol provides for the metadata exchange. But this protocol does not allow vendors to implement metadata for vendor-specific functions.
In addition, using ECC bits to facilitate the exchange of metadata means that those bits are not available for ECC. Thus, allocating ECC bits for use as metadata leads to a weaker ECC system. Compounding the problem is that different systems may require differing numbers of bits for metadata, which in turn affects how many bits are available for error correction.
A need remains for a way to manage the use of ECC bits for both ECC and metadata.